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Design Rule Verification Report

Date : 11/13/2013
Time : 1:10:31 PM
Elapsed Time : 00:00:00
Filename : Z:\ei-hardware\impee-janice-display\impee-janice-display.PcbDoc
Warnings : 0
Rule Violations : 0

Summary

Warnings Count
Total 0

Rule Violations Count
Silk primitive without silk layer 0
Clearance Constraint (Gap=10mil) (IsThruPin and (not PadIsPlated)),(All) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Clearance Constraint (Gap=7mil) (All),(All) 0
Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) 0
Width Constraint (Min=8mil) (Max=100mil) (Preferred=10mil) (All) 0
Routing Layers(All) 0
Routing Via (MinHoleWidth=15mil) (MaxHoleWidth=15mil) (PreferredHoleWidth=15mil) (MinWidth=25mil) (MaxWidth=25mil) (PreferedWidth=25mil) (All) 0
Fabrication Testpoint Usage (Valid =Don't care, Allow multiple per net=No) (All) 0
Fabrication Testpoint Style (Under Component=Yes) (All) 0
Assembly Testpoint Usage (Valid =Don't care, Allow multiple per net=No) (All) 0
Assembly Testpoint Style (Under Component=Yes) (All) 0
Pads and Vias to follow the Drill pairs settings 0
Hole Size Constraint (Min=1mil) (Max=350mil) (All) 0
Differential Pairs Uncoupled Length using the Gap Constraints (Min=10mil) (Max=10mil) (Preferred=10mil) and Width Constraints (Min=15mil) (Max=15mil) (Preferred=15mil) (All) 0
Hole To Hole Clearance (Gap=10mil) (All),(All) 0
Minimum Solder Mask Sliver (Gap=0mil) (All),(All) 0
Silk To Solder Mask (Clearance=1mil) (IsPad),(All) 0
Silk to Silk (Clearance=4mil) (All),(All) 0
Net Antennae (Tolerance=0mil) (All) 0
Total 0