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Design Rule Verification Report

Date : 11/13/2013
Time : 10:58:01 AM
Elapsed Time : 00:00:01
Filename : Z:\ei-hardware\impee-janice\impee-janice.PcbDoc
Warnings : 0
Rule Violations : 0

Summary

Warnings Count
Total 0

Rule Violations Count
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Clearance Constraint (Gap=7mil) (All),(All) 0
Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) 0
Width Constraint (Min=7mil) (Max=50mil) (Preferred=10mil) (All) 0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All) 0
Hole Size Constraint (Min=10mil) (Max=350mil) (All) 0
Hole To Hole Clearance (Gap=7mil) (All),(All) 0
Minimum Solder Mask Sliver (Gap=2mil) (All),(All) 0
Silk To Solder Mask (Clearance=1mil) (IsPad),(All) 0
Silk to Silk (Clearance=7mil) (All),(All) 0
Net Antennae (Tolerance=0mil) (All) 0
Total 0