//=============================================================================
//
//      pci_serv.c - Cyclone Diagnostics
//
//=============================================================================
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// -------------------------------------------                              
// This file is part of eCos, the Embedded Configurable Operating System.   
// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
//
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// for more details.                                                        
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//
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//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):   Scott Coulter, Jeff Frazier, Eric Breeden
// Contributors:
// Date:        2001-01-25
// Purpose:     
// Description: 
//
//####DESCRIPTIONEND####
//
//===========================================================================*/

/********************************************************************************/
/* PCI_SERV.C - PCI driver for IQ80310					        */
/*								    		*/
/* History:                                                                     */
/*  15sep00 ejb Ported to Cygmon on IQ80310				    	*/
/*  18dec00 snc                                                                 */
/********************************************************************************/
#include <redboot.h>
#include <cyg/hal/hal_iop310.h>        // Hardware definitions
#include "iq80310.h"
#include "pci_bios.h"

#undef  DEBUG_PCI

#define	IB_MA_ERROR	0x2000

/*==========================================================================*/
/* Globals                                                                  */
/*==========================================================================*/
ULONG	memspace_ptr[NUM_PCI_BUSES];
ULONG	iospace_ptr[NUM_PCI_BUSES];
ULONG	memspace_limit[NUM_PCI_BUSES];
ULONG	iospace_limit[NUM_PCI_BUSES];
UINT	nextbus;
UINT	secondary_busno = SECONDARY_BUS_NUM;
UINT	primary_busno = PRIMARY_BUS_NUM;
UINT    lastbus;
unsigned long dram_size; /* global storing the size of DRAM */	
int bus0_lastbus;        /* last secondary bus number behind bus 0 */
int bus1_lastbus;        /* last secondary bus number behind bus 1 */

int nmi_verbose;	/* global flag to indicate whether or not PCI Error messages should be
			   printed.  This flag is used to prevent a painful deluge of messages
			   when performing PCI configuration reads/writes to possibly non-existant
			   devices. */

int pci_config_error = FALSE; /* becomes TRUE if an NMI interrupt occurs due to a PCI config cycle */

#define PRINT_ON()  nmi_verbose = TRUE
#define PRINT_OFF() nmi_verbose = FALSE

/*==========================================================================*/
/* Function prototypes                                                      */
/*==========================================================================*/

typedef struct
{
    FUNCPTR	handler;
    int		arg;
    int		bus;
    int		device;
} INT_HANDLER;

#define NUM_PCI_XINTS		4		/* XINT0 - XINT3 */
#define MAX_PCI_HANDLERS	8		/* maximum handlers per PCI Xint */

extern void hexIn(void);
extern int pci_config_cycle;
extern void _enableFiqIrq(void);
extern void config_ints(void);	/* configure interrupts */

/*********************************************************************************
* pci_to_xint - convert a PCI device number and Interrupt line to an 80312 XINT
*
* This function converts a PCI slot number (0 - 7) and an Interrupt line
* (INTA - INTD) to a i960 processor XINT number (0 - 3)
*
* RETURNS: OK or ERROR if arguments are invalid
*
*/
STATUS pci_to_xint(int device, int intpin, int *xint)
{
    int device_base;	/* all devices mod 4 follow same interrupt mapping scheme */

    /* check validity of arguments */
    if ((intpin < INTA) || (intpin > INTD) || (device > 31))
	return (ERROR);

    device_base = device % 4;

    /* interrupt mapping scheme as per PCI-to-PCI Bridge Specification */
    switch (device_base) {
    case 0:
	switch (intpin) {
	case INTA:
	    *xint = XINT0;
	    break;
	case INTB:
	    *xint = XINT1;
	    break;
	case INTC:
	    *xint = XINT2;
	    break;
	case INTD:
	    *xint = XINT3;
	    break;
	}
	break;
    case 1:
	switch (intpin) {
	case INTA:
	    *xint = XINT1;
	    break;
	case INTB:
	    *xint = XINT2;
	    break;
	case INTC:
	    *xint = XINT3;
	    break;
	case INTD:
	    *xint = XINT0;
	    break;
	}
	break;
    case 2:
	switch (intpin) {
	case INTA:
	    *xint = XINT2;
	    break;
	case INTB:
	    *xint = XINT3;
	    break;
	case INTC:
	    *xint = XINT0;
	    break;
	case INTD:
	    *xint = XINT1;
	    break;
	}
	break;
    case 3:
	switch (intpin) {
	case INTA:
	    *xint = XINT3;
	    break;
	case INTB:
	    *xint = XINT0;
	    break;
	case INTC:
	    *xint = XINT1;
	    break;
	case INTD:
	    *xint = XINT2;
	    break;
	}
	break;
    }
    return (OK);
}


/******************************************************************************
*
* Checks to see if the "bus" argument identifies a PCI bus which is located 
* off of the Primary PCI bus of the board.
*/
int off_ppci_bus (int busno)
{
    if (busno == primary_busno) 
	return (TRUE);
    else if (busno == secondary_busno) 
	return (FALSE);
    else if (busno <= bus0_lastbus)
	return (TRUE);
    else
	return (FALSE);
}

/******************************************************************************
* sys_set_pci_irq - connect a PCI interrupt to a processor IRQ.
*
* The PCI Interrupt routing fabric on the Cyclone Hardware is not 
* reconfigurable (fixed mapping relationships) and therefore, this function
* is not supported.
*
*/
STATUS sys_set_pci_irq (int int_pin, int irq_num, int bus_dev)
{
    return (FUNC_NOT_SUPPORTED);
}

/* check if host of backplane */
int isHost(void)
{
    if (*BACKPLANE_DET_REG & BP_HOST_BIT)
	return TRUE;
    else
	return FALSE;
}




